关键词:5/3小波; 提升结构; 静态时序分析; 流水线技术; 现场可编程门阵列
Deeppipeline optimization for lifting architecture of 5/3 DWT
XU Yong1, 2, XU Zhi-yong1, ZHANG Qi-heng1
(1.Institute of Optics & Electronics, Chinese Academy of Sciences, Chengdu 610209, China; 2.Graduate School, Chinese Academy of Sciences, Beijing 100039, China)
Abstract:To realize higher speed 5/3 discrete wavelet transform (DWT) for the demands of realtime high speed signals processing based on DWT. This paper studied speed limit factors in current 5/3 DWT architecture by using static timing analysis, then redesigned the current architecture with pipeline technique to break through the overlong strict path. Experiment results indicate that at the price of increasing a few cost of registers, proposed 5/3 DWT architecture’s maximum frequencies are speed up to 250% of original architecture, and can achieve a maximum speed of 300 MSPS(million samples per second). This architecture can be used in high performance waveletbased signal processing applications on FPGA. ......